It is known that, in a semiconductor chip manufactured by advanced semiconductor process of a design rule of less than 90 nm, power consumption of a semiconductor device corresponds to a sum of operating power and leak power.
The operating power depends on a magnitude of an input voltage to the semiconductor chip and rarely varies among semiconductor chips depending on variation in the semiconductor manufacturing process. The operating power and the power consumption of the semiconductor device increase as the input voltage of the same increases.
The leak power depends on current characteristic of the semiconductor chip, that is, a magnitude of a threshold voltage of a transistor. The leak power therefore varies among semiconductor chips depending on variation in the semiconductor manufacturing process. Since a leak current increases as the threshold voltage decreases, a semiconductor chip having larger leak power has better switching characteristic in comparison with a semiconductor chip having smaller leak power.
It is therefore possible to reduce the power consumption of the semiconductor chip and maintain a switching frequency of the semiconductor chip substantially unchanged, by lowering the input voltage of a semiconductor chip having larger leak power to be less than that of a semiconductor chip having smaller leak power.
This is described in more detail with reference to FIG. 9. In FIG. 9, (a) and (b) schematically show details of power consumption Pc as a sum of operating power Po and leak power PI with respect to two semiconductor chip samples A and B, respectively. It is assumed that the samples A and B are manufactured by the same manufacturing process, that the leak powers PI of the samples A and B are assumed to be small and large, respectively, and that same input voltages are applied to the samples A and B.
As understood from (a) and (b) of FIG. 9, the operating powers Po are generally the same between the samples A and B but the sample B has larger leak power PI than the sample A. Therefore, the threshold voltage Vth of the sample B is lower than that of the sample A, and a limit value of an operating frequency (that is, operable switching frequency) of the sample B is higher than that of the sample A.
It is thus proposed to lower the input voltage to the sample B so that its power consumption Pc is lowered from a power level Pb to a power level Pa of the sample A as shown by (c) in FIG. 8, while maintaining the limit value of its operating frequency at generally the same limit value of the operating frequency of sample A.
This technology (VID: dynamic-voltage identification), which uses the above-described chip characteristic, is disclosed in the following non-patent document.    Intel Corp., “Voltage Regulator-Down (VRD) 11.0”, pp. 27-28, November, 2006
According to this VID technology, as shown in FIG. 10, a voltage control system 100 is configured with a semiconductor package 110 and a power supply LSI (PS-LSI) 120. The semiconductor package 110 includes a CPU 111 and a non-volatile memory 112 and is integrated by using the application specific standard produce (ASSP). The CPU 111 and the non-volatile memory 112 correspond to semiconductor chips. The power supply LSI 120 includes a DC-DC converter 121. The semiconductor package 110 and the power supply LSI 120 are connected to perform serial communications and supply electric power from the power supply LSI 120 (specifically DC-DC converter 121) to the semiconductor package 110.
In the voltage control system 100, an operating power and a limit value of operating frequency of the semiconductor package 110 are tested after manufacture. A voltage value (VID) is determined based on the test result and stored in the non-volatile memory 112. The DC-DC converter 121 of the power supply LSI 120 is configured to, acquire the VID from the semiconductor package 110 by way of serial communications and set an input voltage to the semiconductor package 110 in accordance with the acquired VID. Thus, the voltage control system 100 saves power consumption of the semiconductor package 110.
According to the conventional technology, however, the voltage value (VID) need be stored in each semiconductor chip in a semiconductor chip test process. As a result, the semiconductor chip test process is complicated and increases cost. In case of integrating a plurality of semiconductor chips (Sip: system in package), the semiconductor chip test process is more complicated.